The present invention relates to a semiconductor memory having a plurality of data input/output terminals, and more specifically to a semiconductor memory having a plurality of mask/disable terminals and executing a mask/disable operation for inhibiting data write/read to and from a corresponding data input/output terminal according to each mask/disable control signal.
A semiconductor memory as represented by a RAM (Random Access Memory) or a ROM (Read Only Memory) has a plurality of data input/output terminals corresponding to a plurality of bits to enable storage of a large capacity of data and high speed operations for writing or reading data. Of the memories as described above, there are ones each having a mask/disable terminal for inhibiting operations for writing or reading data.
In recent years, various types of semiconductor memory module having a plurality of packaged semiconductor memories (described as semiconductor memory device hereinafter) for realization of a larger storage capacity have been introduced into the market. In this type of semiconductor memory module, a common data bus is shared by a plurality of semiconductor memory devices, and in that case, permission of operations for writing or reading data should be made for each semiconductor memory, and data input/output with high flexibility has been enabled by using the semiconductor memory having a plurality of mask/disable terminals as the semiconductor memory device.
A semiconductor memory comprising a synchronous dynamic RAM having mask/disable terminals and operating in synchronism to an external clock (described as SDRAM hereinafter) as one example of the conventional technology will be described. FIG. 16 is a block diagram showing general configuration of a semiconductor memory based on the conventional technology. FIG. 16 especially shows a SDRAM based on the memory bank system enabling management of a memory capacity larger than the address space of a MPU by utilizing a MPU (Micro Processing Unit).
In FIG. 16, SDRAM 100 comprises memory arrays each in turn comprising memory cells as memory units in a matrix form, and the memory arrays are divided into two banks (bank 0, bank 1) with each bank further divided into a plurality of blocks. Each bank has a row decoder 102 and a column decoder 103, and one memory cell is selected from a memory array 101 by the decoders 102, 103. The row decoder 102 is a circuit that receives a row address signal 110 and selects one word line from those each identifying a memory cell in the row direction. The column decoder 103 is a circuit that receives a column address signal 111 and selects one bit line from those each identifying a memory. cell in the column direction. A sense amplifier 104 for amplifying an electric charge stored in a memory cell is connected to each bit line.
Data in a memory cell identified by the row decoder 102 and column decoder 103 according to a data read command in the bank 0 or bank 1 is inputted via a global database (GDB) into a write amplifier/sense buffer 105. In this SDRAM 100, input/output of data comprising a plurality of bits is capable, and for instance when input/output of 16-bit data is to be executed, 2-byte data for a memory cell identified according to inputted row address signal 110 as well as according to inputted column address signal 111 is latched in the write amplifier/sense buffer 105 for parallel output of data.
The read data latched in the write amplifier/sense buffer 105 is transferred to an I/O data buffer/register 107 and it is outputted from data input/output terminals DQ0 to DQn of the I/O data buffer/register 107.
When a data write command is received, write data is sent from the write amplifier/sense buffer 105 via the GDB 106 to a memory cell identified by the row decoder 102 and column decoder 103. The write data is inputted from data input/output terminal DQ0 to DQn of the I/O data buffer/register 107 and transferred to the write amplifier/sense buffer 105.
The row address signal 110 and column address signal 111 are generated according to signals inputted from address terminals A0 to An of an address buffer/register and bank select 108.
A RAS signal 120, a CAS signal 121 and a WE signal 122 are inputted into the bank 0 or bank 1, and a control instruction such as a write instruction or a read instruction is decided according to a combination of these three signals. Especially, functions of the write amplifier/sense buffer 105 are decided according to the control instruction.
The RAS signal 120, CAS signal 121 and WE signal 122 inputted into the bank 0 or bank 1 are outputted from a control signal latch 113. The control signal latch 113 receives a command signal 125 from a command decoder 112, latches a control signal indicated by the command signal 125, and outputs the RAS signal 120, CAS signal 121 and WE signal 122 each as a signal level capable of expressing a control instruction according to a combination of the signals.
A command decoder 112 receives a /CS signal, a /RAS signal, a /CAS signal and a /WE signal, decides a control instruction according to a combination of these signals, and outputs a command instruction indicating the control instruction. The command decoder 112 also decides an access mode according a combination of the /CS signal, /RAS signal, /CAS signal and /WE signal, and outputs a mode signal 126 indicating the access mode.
The mode register 114 receives the mode signal 126 and address signals A0 to An transferred via the address buffer/register and bank selector 108 and temporally stores therein the signals. The column address counter 109 determines an access mode such as a burst read mode according to the mode signal and address signal stored in the mode register 114, and generates and outputs the column address signal 111 corresponding to the determined access mode.
The SDRAM 100 operates according to a synchronous signal (CLK) given from the outside such as a system clock from the MPU, and can executes operations in the internal circuit described above at a high speed. A clock buffer 115 receives a clock signal (CLK) given from the outside and a clock enable signal (CKE) controlling output of the clock signal, and supplies the received clock signal to each of the circuits described above. The clock buffer 115 also provides the received clock enable signal to each of the command decoder 112, address buffer/register and bank select 108 and I/O data buffer/register 107.
The I/O data buffer/register 107 receives a mask/disable signal from the mask/disable terminal described above. Specifically the I/O data buffer/register 107 receives a DQMU signal which is a signal for masking/disabling upper bits of the data signals DQ0 to DQn from the DQMU terminals, and also receives a DQML signal which is a signal for masking/disabling lower bits of the data signals DQ0 to DQn from the DQML terminal.
The DQMU signal and DQML signal are sent as MASK0 and MASK1 signals to the bank 0 and bank 1 respectively, and are inputted into the write amplifier/sense buffer 105 in each bank. When the DQMU signal (MASK1) indicates a xe2x80x9cHxe2x80x9d level and a control instruction given to the bank 0 and bank 1 is a write instruction, the write amplifier/sense buffer 105 masks data corresponding to upper bits of the data signals DQ0 to DQn, namely an operation for writing the data into the write amplifier/sense buffer 105 is inhibited. When the DQML signal (MASK0) indicates the xe2x80x9cHxe2x80x9d level and a control instruction given to the bank 0 and bank 1 is a write instruction, the write amplifier/sense buffer 105 masks data corresponding to lower bits of the data signals DQ0 to DQn, namely an operation for writing the data into the write amplifier/sense buffer 105 is inhibited.
When the DQMU signal indicates a xe2x80x9cHxe2x80x9d level and a control instruction given to the bank 0 and bank 1 is a read instruction, the write amplifier/sense buffer 105 masks data corresponding to lower bits of the data signals DQ0 to DQn, namely an operation for reading the data from the write amplifier/sense buffer 105 is inhibited. When the DQML signal indicates a xe2x80x9cHxe2x80x9d level and a control instruction given to the bank 0 and bank 1 is a read instruction, the write amplifier/sense buffer 105 masks data corresponding to lower bits of the data signals DQ0 to DQn, namely an operation for reading data from the write amplifier/sense buffer 105 is inhibited.
FIG. 17 is an explanatory view showing key sections of a semiconductor memory according to the conventional technology, and shows configuration of a data input/output section of the SDRAM according to the conventional technology. The I/O data buffer/register 107 shown in FIG. 16 is actually divided, as shown in FIG. 17, into an I/O data buffer 131 connected to the data input/output terminals for data signals DQ0 to DQ15 and DQM input buffers 132 and 133 connected to mask terminals for the DQML and DQMU signals respectively.
The write amplifier/sense buffer 105 shown in FIG. 16 is actually divided, as shown in FIG. 17, into write amplifier/sense buffers 141 corresponding to the data input/output terminals for the data signals DQ0 to DQ15. Further, the DQM input buffer 132 is connected to eight units of write amplifier/sense buffers 141 corresponding to the data signals DQ0 to DQ7, while the DQM input buffer 133 is connected to 8 units of write amplifier/sense buffers 141 corresponding to the data signals DQ8 to DQ15.
Because of this configuration, when a data write instruction is given to a bank, more specifically to the write amplifier/sense buffers 141, each of data inputted into the data input/output terminals DQ0 to DQ15 is inputted via the I/O data buffer 131 into the write amplifier/sense buffers 141 and then is sent to the GDB 106.
In this step, when a mask/disable signal inputted from the DQML terminal indicates a xe2x80x9cHxe2x80x9d level, namely inhibition of an operation for writing data, data transfer from the write amplifier/sense buffers 141 corresponding to the data input/output terminals DQ0 to DQ7 to the GDB 106 is not executed. Similarly, when a mask/disable signal inputted from the DQMU terminal indicates a xe2x80x9cHxe2x80x9d level, data transfer from the write amplifier/sense buffers 141 corresponding to the data input terminals DQ8 to DQ15 is not executed.
When a data read instruction is given to a bank, more specifically to the write amplifier/sense buffer 141, data in memory cells successively identified according to the row address signal 110 and column address signal 111 is sent to the GDB 106 and inputted to the write amplifier/sense buffer 141 connected to each GDB 106. Data inputted to each write amplifier/sense buffer 141 is sent to each corresponding I/O data buffer 131 and is outputted from the data input/output terminals DQ0 to DQ15.
In this step, when a mask/disable signal inputted from the DQML terminal indicates a xe2x80x9cHxe2x80x9d level, namely inhibition of an operation for reading data, data transfer from the write amplifier/sense buffers 141 corresponding to the data input/output terminals DQ0 to DQ7 to the I/O data buffer 131 is not executed. When a mask/disable signal inputted from the DQMU terminal indicates a xe2x80x9cHxe2x80x9d level, data transfer from the write amplifier/sense buffers 141 corresponding to the data input/output terminals DQ8 to DQ15 to the I/O data buffer 131 is not executed.
Next, detailed description is made for the write amplifier/sense buffers 141. FIG. 18 is a view showing connection among the write amplifier/sense buffers 141, I/O data buffer 131, and DQM input buffer 132. FIG. 18 especially shows configuration relating to the data input/output terminal DQ0, but any of the other data input/output terminal DQ1 to DQ15 has the same configuration. As shown in FIG. 18, the write amplifier/sense buffer 141 is actually divided into a sense buffer 151 and a write amplifier 152. In the write amplifier/sense buffer 141, the sense buffer 151 operates in response to a data read instruction, receives read data (Rdata 0/1) sent to the GDBs (GDB0, GDB1) and sends the received read data to the I/O data buffer 131. The sense buffer 151 also received a mask/disable signal (MASK0) outputted from the DQM input buffer 132, and executes an operation for disabling data read in response to a signal level of the MASK0 signal.
On the other hand, in the write amplifier/sense buffer 141, the write amplifier 152 operates in response to a data write instruction, receives write data (Wdata) outputted from the I/O data buffer 131, and sends the received write data to the GDBs (GDB0, GDB1). The write amplifier 152 receives the mask/disable signal (MASK0) outputted from the DQM input buffer 132, and executes an operation for masking against data write in response to a signal level of the MASK0 signal.
In a DRAM such as a SDRAM, generally a signal level of one data is determined by comparing signal levels of complimentary data signals each other, so that a signal level of data sent to the GDB 106 is decided by the two signals GDB0 and GDB1, and herein description is made assuming that a signal level of GDB0 against a level of a signal sent to the GDB1 is a signal level of data inputted to or outputted from the I/O data buffer 131.
Next, detailed description is made for the sense buffer 151. FIG. 19 is an explanatory view showing circuit configuration of the sense buffer 151. In FIG. 19, the sense buffer 151 comprises two transfer gates SW100 and SW101, three switching elements (herein, FET elements) TR100, TR101 and TR102, three inverters 161, 163 and 166, and three NAND gates 162, 164 and 165.
The sense amplifier 104 is connected to the GDB0 and GDB1 in turn connected to the sense buffer 151 respectively, and data is sent from this sense amplifier to the GDB0 and GDB1.
The read data Rdata0 signal and Rdata1 signal each outputted from the sense buffer 151 indicates the same signal level respectively, and the signals are inputted into the I/O data buffer data 131. In the sense buffer 151, the Rdata0 signal is outputted from a NAND gate 164, while the Rdata1 signal is outputted from an inverter 166. The inverter 166 has the input terminal connected to an output terminal of the NAND gate 165. Further, one input terminal of the NAND gate 164 is connected to an output terminal of the NAND gate 165, while an input terminal of the NAND gate 165 is connected to an output terminal of the NAND gate 164. Because of this configuration, a signal level of Rdata0/1 depends on a signal level of signals inputted to the other input terminal of the NAND gate 164 and the other input terminal of the NAND gate 165 respectively.
The other input terminal of the NAND gate 164 is connected to one of contact terminals of the transfer gate SW100 as well as to a D terminal of the switching element TR100. The other input terminal of the NAND gate 165 is connected to the other contact terminal of the transfer gate SW101 as well as to a D terminal of the switching element TR101. The other contact terminals of the transfer gate SW100 and SW101 are connected to a power terminal indicating a xe2x80x9cHxe2x80x9d level respectively, so that a level of a signal inputted to the other input terminal of the NAND gate 164 and that of the NAND gate 165 is decided by ON/OFF state of the transfer gates SW100, SW101 and switching elements TR100 and TR101. Namely, a signal level of the Rdata0 signal and Rdata1 signal (Rdata0/1) is decided according to ON/OFF state of the transfer gates SW100, SW101 and switching elements TR100, TR101.
The output terminals of both of the transfer gates SW100 and SW101 are connected to an output terminal of the inverter 163. An output terminal of the NAND gate 162 and an input terminal of the inverter 163 are connected to each other. The NAND gate 162 receives a control signal (READ) indicating a data read instruction from one of the input terminals and receives an output signal from the inverter 161 from the other input terminal. The inverter 161 receives the MASK0 signal outputted from the DQM input buffer 132 and outputs the inverted signal. Because of this configuration, ON/OFF of the transfer gates SW100 and SW101 is controlled according to a level of a signal outputted from the NAND gate 162, namely according to the READ signal and MASK0 signal.
On the other hand, the switching element TR100 has the G terminal connected to the GDB0, while the switching element TR101 has the G terminal connected to the GDB1. Namely, ON/OFF of the switching elements TR100 and TR101 is controlled according to a signal level of the signals sent to the GDB0 and GDB1. Both of S terminals of the switching elements TR100 and TR101 are connected to a D terminal of the switching element TR102. The switching-element TR102 has the S terminal connected to a electric potential indicating a xe2x80x9cLxe2x80x9d level, and when the switching element TR100 is ON, namely when a signal with a signal level higher than a threshold level (herein, xe2x80x9cHxe2x80x9d levelxe2x80x9d for the switching element TR100 is inputted to the G terminal of the switching element TR100, and simultaneously when the switching element TR102 is ON, namely when a signal with a signal level higher than a threshold level (herein, xe2x80x9cHxe2x80x9d level) for the switching element TR102 is inputted to the G terminal of the switching element TR102, the D terminal of the switching element TR101 is set in a xe2x80x9cLxe2x80x9d level potential. In other words, a signal with the xe2x80x9cLxe2x80x9d signal level is inputted to the other input terminal of the NAND gate 164.
When the switching element TR101 is ON, namely when a signal with a signal level higher than a threshold level (herein, xe2x80x9cHxe2x80x9d level) for the switching element TR101 is inputted to the G terminal of the switching element TR101, and simultaneously when the switching element TR102 is one, namely when a signal with a signal level higher than a threshold level (herein, xe2x80x9cHxe2x80x9d level) for the switching element TR101 is inputted to the G terminal of the switching element TR102, the D terminal of the switching element TR101 is set in a xe2x80x9cLxe2x80x9d level potential. In other words, a signal with the xe2x80x9cLxe2x80x9d signal level is inputted to the other input terminal of the NAND gate 165.
An output terminal of the inverter 163 is connected to the G terminal of the switching element TR102, and ON/OFF state of the switching element TR102 is controlled according to the READ signal as well as to the MASK0 signal.
Namely, during an operation for reading out data, when the READ signal is set in a xe2x80x9cHxe2x80x9d level, the transistor TR102 is turned ON with a differential amplifier comprising the transistors TR100 and TR101 activated, and data for the GDB1 and GDB0 is outputted as Rdata0 and Rdata1 respectively. Even during the operation for reading out data, when the mask signal MASK0 is set in a xe2x80x9cHxe2x80x9d level, the transistor TR102 is turned OFF, and data for the GDB1 and GDB0 is not outputted from the differential amplifier.
FIG. 20 is a time chart for signals inputted into and outputted from the sense buffer 151 (signals sent to the GDB0 and GDB1, READ signal, MASK0 signal, Rdata0 signal and Rdata1 signal).
At first in a period of pulse generation for a first READ signal (period (1)), or to describe more precisely, in a first transition of a pulse for the first READ signal, when the MASK0 signal indicates a xe2x80x9cLxe2x80x9d level, namely when an operation for disabling data read is not executed, output from the NAND gate 162 indicates a xe2x80x9cLxe2x80x9d level with the inverter 163 indicating a xe2x80x9cHxe2x80x9d level if a signal on the GDB0 indicates a xe2x80x9cHxe2x80x9d level and simultaneously a signal on the GDB1 indicates a xe2x80x9cLxe2x80x9d level, and both the transfer gates SW100 and SW101 are turned ON. Further, the switching element TR100 is turned ON. Then a signal on the GDB0 indicates a xe2x80x9cHxe2x80x9d level with the switching element TR100 turned ON, and a signal with a xe2x80x9cLxe2x80x9d level is inputted to the other input terminal of the NAND gate 164. Namely the NAND gate 164 outputs a signal with a xe2x80x9cHxe2x80x9d level as the Rdata0 signal.
When a signal on the GDB1 indicates a xe2x80x9cLxe2x80x9d level, the switching element TR101 is turned OFF, and a signal with a xe2x80x9cHxe2x80x9d level supplied from the transfer gate SW101 is inputted to the other input terminal of the NAND gate 165. Herein, a signal with the xe2x80x9cHxe2x80x9d level outputted from the NAND gate 164 is inputted to the other input terminal of the NAND gate 165, so that the NAND gate 165 outputs a signal with a xe2x80x9cLxe2x80x9d level. A signal outputted from the NAND gate 165 is inverted by the inverter 166 and outputted as the Rdata1 signal, so that, in this case, also the Rdata1 signal indicates a xe2x80x9cHxe2x80x9d level like the Rdata0 signal.
Next, in a period of pulse generation for a second READ signal (period (2)), or to described more precisely, in a first transition of a pulse for the second READ signal, when the MASK0 signal indicates a xe2x80x9cLxe2x80x9d level and simultaneously the GDB0 signal indicates a xe2x80x9cLxe2x80x9d level, namely when a signal on the GDB1 indicates a xe2x80x9cHxe2x80x9d level, output from the NAND gate 162 (xe2x80x9cLxe2x80x9d level) and output from the inverter 163 (xe2x80x9cHxe2x80x9d level) do not change with both the transfer gates SW100 and SW101 turned ON, while the switching element TR102 is kept ON. A difference between the period (1) is that, when a signal on the GDB0 indicates a xe2x80x9cLxe2x80x9d level, the switching element TR100 is turned OFF, and a signal with a xe2x80x9cHxe2x80x9d level supplied from the transfer gate SW100 is inputted to the other input terminal of the NAND gate 164.
When a signal on the GDB1 indicates a xe2x80x9cLxe2x80x9d level, the switching element TR101 is turned ON, and a signal with a xe2x80x9cLxe2x80x9d level is inputted to the other input terminal of the NAND gate 165. Namely, the NAND gate 165 outputs a signal with a xe2x80x9cHxe2x80x9d level. A signal outputted from the NAND gate 165 is inverted by the inverter 166 and outputted as the Rdata1 signal, and in this case the Rdata1 signal indicates a xe2x80x9cLxe2x80x9d level. Herein one input terminal of the NAND gate 164 receives a signal with a xe2x80x9cHxe2x80x9d level outputted from the NAND gate 165, so that the NAND gate 164 outputs a signal with a xe2x80x9cLxe2x80x9d level as the Rdata0 signal.
When the MASK0 signal indicates a xe2x80x9cLxe2x80x9d level, namely when an operation of disabling data read is not executed, the Rdata0 signal and Rdata1 signal indicates the same signal level as that of the signal sent to the GDB0 and are sent to the I/O data buffer 131.
In a period of pulse generation for a third READ signal (period (3)), or to described more precisely, when the MASK0 signal indicates a xe2x80x9cHxe2x80x9d level, namely when an operation for disabling data read is executed, if a signal of the GDB0 indicates a xe2x80x9cHxe2x80x9d level and simultaneously a signal on the GDB1 indicates a xe2x80x9cLxe2x80x9d level, output from the NAND gate 162 indicates a xe2x80x9cHxe2x80x9d level and the inverter 163 indicates a xe2x80x9cLxe2x80x9d level, so that both the transfer gates SW100 and SW101 are turned OFF. Further, the switching element TR102 is turned OFF. When a signal on the GDB0 indicates a xe2x80x9cHxe2x80x9d level, the switching element TR100 is turned ON, but the switching element TR102 is in OFF state, in addition, a xe2x80x9cHxe2x80x9d level potential is not supplied from the transfer gate SW100, so that a level of a signal inputted to the other input terminal of the NAND gate 164 becomes unstable.
When a signal on the GDB1 indicates a xe2x80x9cLxe2x80x9d level, the switching element TR100 is turned OFF, but a potential with a xe2x80x9cHxe2x80x9d level is not supplied from the transfer gate SW101, so that a level of a signal inputted to the other input terminal of the NAND gate 165 becomes unstable.
Therefore, output from the NAND gates 164 and 165 does not change, and a level of the Rdata0 signal and Rdata1 signal is not changed. With this feature, an operation for disabling data read is achieved. In FIG. 20, a portion indicated by the dotted lines is a signal not outputted because of the disabling operation.
In a period of pulse generation for a fourth READ signal (period (4)), or to described more precisely, the MASK0 signal again indicates a xe2x80x9cLxe2x80x9d level, and the same state as that in the period (2) is effected.
Next, detailed description is made for the write amplifier 152. FIG. 21 is an explanatory view showing circuit configuration of the write amplifier 152. In FIG. 21, the write amplifier 152 comprises two transfer gates SW110 and SW111, five inverters 171, 173, 174, 175 and 176, and one NAND gate 172.
The GDB0 and GDB1 connected to the write amplifier 152 are further connected to the sense amplifier 104, and write data in the sense amplifier 104 according to a write signal sent to the GDB0 and GDB1.
Write data Wdata outputted from the I/O data buffer 131 is inputted to the inverter 174 as a write amplifier with the signal level inverted therein and then the signal is outputted. An output terminal of the inverter 174 is connected to one contact terminal of the transfer gate SW110 and also to an input terminal of the inverter 175. Herein the contact terminal of the transfer gate SW110 is connected to the GDB1, and when the transfer SW110 is ON, the Wdata signal with the signal level inverted is sent to the GDB1.
An output terminal of the inverter 175 is connected to one contact terminal of the transfer gate SW111. The other contact terminal of the transfer gate SW1 is connected to the GDB0, and when the transfer gate SW111 is ON, a signal with the same level as that of the Wdata signal is sent to the GDB0.
With the two inverters 174 and 175, it is possible to send two types of signals, namely two signals with mutually inverted levels to the GDB0 and GDB1 in response to one write data Wdata.
One control terminal of the transfer gate SW110 is connected to an output terminal of the inverter 173, and the other control terminal is connected to an output terminal of the inverter 176. An input terminal of the inverter 176 is also connected to an output terminal of the inverter 173, so that the ON/OFF of the transfer gate SW110 is controlled according to a level of a signal outputted from the inverter 173.
The other input control terminal of the transfer gate SW111 is connected to an output terminal of the inverter 173, and also the other output terminal is connected to an output terminal of the inverter 176. With this configuration, like in the transfer gate SW110, also the ON/OFF of the transfer gate SW111 is controlled according to a level of a signal outputted from the inverter 173.
An input terminal of the inverter 173 is connected to an output terminal of the NAND gate 172. The NAND gate 172 receives a control signal (WE) indicating a data write instruction from one input terminal thereof, and receives an output signal from the other input terminal. The inverter 171 receives the MASK0 signal outputted from the DQM buffer 132, and outputs the inverted signal. Because of this configuration, ON/OFF of the transfer gates SW110 and SW111 is controlled according to a level of a signal outputted from the NAND gate 172, namely to the READ signal and MASK0 signal.
Therefore, the level of signals on the GDB0 and GDB1 changes according to the Wdata signal, WE signal and MASK0 signal. Namely, when the WE signal is set in a xe2x80x9cHxe2x80x9d level in data write, the transfer gates SW110 and SW111 are turned ON, and write data outputted from the write amplifier 174 is sent to the GDB1 and GDB0. On the other hand, when the MASK0 signal is at a xe2x80x9cLxe2x80x9d level in this step, the transfer gates SW110 and SW111 are turned OFF, and transmission of data write from the write amplifier 174 to the GDB1 and GDB0 is inhibited.
FIG. 22 is a time chart for signals inputted to or outputted from the write amplifier 152 (Wdata signal, WE signal, MASK0 signal, and signals sent to the GDB0 and GDB1).
At first, in a period of pulse generation for a first WE signal (period (1)), or to describe more precisely in a first transition of a pulse for the first WE signal, when the MASK0 signal indicates a xe2x80x9cLxe2x80x9d level, namely when a masking operation against data write is not executed, if the Wdata signal indicates a xe2x80x9cLxe2x80x9d level, output from the NAND gate 172 indicates the xe2x80x9cLxe2x80x9d level, while the inverter 173 indicates a xe2x80x9cHxe2x80x9d level, and both the transfer gates SW110 and SW111 are turned ON.
As the Wdata signal indicates a xe2x80x9cLxe2x80x9d level, a xe2x80x9cHxe2x80x9d level signal obtained by inverting the signal by the inverter 174 is sent via the transfer gate SW110 to the GDB1. In addition, a signal indicating a xe2x80x9cHxe2x80x9d level outputted from the inverter 174 is inputted to and inverted by the inverter 175, and is sent as a signal indicating a xe2x80x9cLxe2x80x9d level via the transfer gate SW111 to the GDB0.
In a period for pulse generation for a second WE signal (period (2)), or to describe more precisely, in a first transition of a pulse for the second WE signal, in the state where the MASK0 signal indicates a xe2x80x9cLxe2x80x9d level and at the same time the Wdata signal indicates a xe2x80x9cHxe2x80x9d level, output (xe2x80x9cLxe2x80x9d level) from the NAND gate 172 and output (xe2x80x9cHxe2x80x9d level) from the inverter 173 do not change, and both the transfer gates SW100 and SW101 are turned ON. A difference between the period (1) is that, when the Wdata signal indicates a xe2x80x9cHxe2x80x9d level, a signal indicating the inverted xe2x80x9cLxe2x80x9d level is sent from the inverter 174 via the transfer gate SW110 to the GDB1 and a signal indicating the inverted xe2x80x9cHxe2x80x9d level is sent from the inverter 175 via the transfer gate SW111 to the GDB0.
In a period of pulse generation for a third WE signal (period (3)), or to describe more precisely, in a first transition of a pulse for the third WE signal, when the MASK0 signal indicates a xe2x80x9cHxe2x80x9d level, namely when a masking operation against data write is executed, if the Wdata signal indicates a xe2x80x9cLxe2x80x9d level, output from the NAND gate 172 indicates a xe2x80x9cHxe2x80x9d level irrespective of a level of the WE signal, the inverter 173 indicates a xe2x80x9cLxe2x80x9d level, and both the transfer gates SW110 and SW111 are turned OFF. Because of this configuration, signals outputted from the inverters 174 and 175 are not sent to the DGB1 and GDB0 respectively. Namely, the Wdata signal can not be sent to the GDB as write data, and because of this configuration, a masking operation against write data is executed. In FIG. 22, a portion indicated by dotted lines is a signal not inputted because of the masking operation.
Then in a period of pulse generation for a fourth signal (period (4)), or to describe more precisely, in a first transition of a pulse for the fourth WE signal, the MASK0 signal again indicates a xe2x80x9cLxe2x80x9d level, and the effect like that in the period (2) is obtained.
The sense buffer 151 receives a mask/disable signal (MASK0) outputted from the DQM input buffer 132 and executes an operation for disabling read data, but the operation for disabling read data can also be executed by controlling the I/O data buffer 131.
FIG. 23 is an explanatory view showing connection among the write amplifier/sense buffer 141, a I/O data buffer 131a in which it is possible to perform disable operation, and DQM input buffer 132. FIG. 23 especially shows configuration relating to the data input/output terminal DQ0, but any of other data input/output terminals DQ1 to DQ15 has the same configuration.
In the write amplifier/sense buffer 141, the write amplifier 152 has the configuration and executes the operations as shown in FIG. 21 and FIG. 22, but, different from the sense buffer 151 in FIG. 19, the sense buffer 151a does not receives the MASK0 signal, and the configuration comprising the inverter 161 and NAND gate 162 is required to be replaced with an inverter for receiving a RAED signal and inputting the inverted signal to the inverter 163 as well as to other control terminals of the transfer gates SW100 and SW101.
As shown in FIG. 23, the I/O data buffer 131a receives the mask/disable signal (MASK0) outputted from the buffer 132 and executes an operation for disabling data read according to a signal level of the MASK0 signal.
Next, detailed description is made for the I/O data buffer 131a. FIG. 24 is an explanatory view showing circuit configuration of the I/O data buffer 131a. Especially, FIG. 24 shows circuit configuration functioning when read data is outputted to a data input/output terminal. In FIG. 24, the I/O data buffer 131a comprises two transfer gates SW120 and SW121, two switching elements (herein, FET elements) TR120 and TR121, eight inverters 181, 184 to 190, one NAND gate 182, and one NOR gate 183.
The I/O data buffer 131a receives read data Rdata0 and Rdata 1 (each indicating the same signal level) outputted from the sense buffer 151a, and when the MASK0 signal outputted from the DQM input buffer 132 indicates a xe2x80x9cLxe2x80x9d level, outputs read data to the data input/output terminal DQ0 according to the signals indicated by the Rdata0 and Rdata1. On the other hand, when the MASK0 signal indicates a xe2x80x9cHxe2x80x9d level, Rdata0 and Rdata1 are prevented from passing through the NAND gate 182 and NOR gate 183 with both the TR120 and TR121 turned OFF, and the DQ0 is set in a high impedance (Hi-z) state.
At first, in the I/O data buffer 131a, the Rdata0 signal is inputted into one input terminal of the NAND gate 182. The other input terminal of the NAND gate 182 is connected to an output terminal of the inverter 181. The inverter 181 receives the MASK0 signal and outputs the inverted signal. With this configuration, the NAND gate 182 functions as an inverter for the Rdata0 signal when the MASK0 signal indicates a xe2x80x9cLxe2x80x9d level.
An output terminal of the NAND gate 182 is connected to one contact terminal of the transfer gate SW120, while the other contact terminal of the transfer gate SW120 is connected to an input terminal of the inverter 185. The inverter 185 outputs an inverted signal of a signal received from the transfer gate SW120, and inputs the inverted signal to an inverter 189. The inverter 185 has the output terminal connected to an input terminal of the inverter 186, and also has the input terminal connected to an output terminal of the inverter 186. Namely, because of the configuration comprising the inverter 185 and inverter 186, a latch function against a signal outputted from the other contact terminal of the transfer gate SW120 is realized.
An output terminal of the inverter 185 is connected to an input terminal of the inverter 189, and a signal outputted from the inverter 185 is inverted by the inverter 189. An output terminal of the inverter 189 is connected to a G terminal of the switching element TR120. The switching element TR120 is turned ON or OFF according to a signal level at the G terminal.
On the other hand, the Rdata1 signal is inputted to one input terminal of the NOR gate 183. The other input terminal of the NOR gate 183 receives the MASK0 signal. Thus, the NOR gate 183 functions as an inverter against the Rdata1 signal when the MASK0 signal indicates a xe2x80x9cLxe2x80x9d level.
An output terminal of the NOR gate 183 is connected to one contact terminal of the transfer gate SW121, while the other contact terminal of the transfer gate SW121 is connected to an input terminal of the inverter 187. The inverter 187 outputs an inverted signal of a signal inputted from the transfer gate SW121, and inputs the inverted signal to the inverter 190. Herein the inverter 187 has the output terminal connected to an input terminal of the inverter 188, and has the input terminal connected to an output terminal of the inverter 188. Namely, because of the configuration comprising the inverter 187 and inverter 188, a latch function against a signal outputted from the other contact terminal of the transfer gate SW121 is realized.
An output terminal of the inverter 187 is connected to an input terminal of the inverter 190, and a signal outputted from the inverter 187 is inverted by an inverter 190. An output terminal of the inverter 190 is connected to a G terminal of the switching element TR121. The switching element TR121 is turned ON or OFF according to a signal level at the G terminal.
The switching element TR120 has the D terminal connected to a potential VCC indicating a xe2x80x9cHxe2x80x9d level and the S terminal connected to the data input/output terminal DQ0 as well as to a D terminal of the switching element TR121. The switching element TR121 has the S terminal connected to a potential VSS indicated a xe2x80x9cLxe2x80x9d level. With this configuration, when the switching element TR121 is turned ON, a signal outputted to the data input/output terminal DQ0 indicates a xe2x80x9cLxe2x80x9d level at the same potential as the potential VSS. When the switching element TR121 is turned ON and at the same time the switching element TR121 is turned OFF, a signal outputted to the data input/output terminal DQ0 indicates a xe2x80x9cHxe2x80x9d level at the same potential as the potential VCC.
Also the clock signal (CLK) described above is inputted to the I/O data buffer 131a, and this clock signal (CLK) is inputted to one control terminal of each of the transfer gates SW120 and SW121. Further, an output terminal of the inverter 184 is connected to the other control terminal of each of the transfer gates SW120 and SW121, and the clock signal (CLK) is inputted to an input terminal of the inverter 184. With this configuration, the transfer gates SW120 and SW121 are repeatedly turned ON and OFF in synchronism to the clock signal (CLK). Therefore, the level of a signal outputted to the data input/output terminal DQ0 changes according to the MASK0 signal, Rdata0 signal and Rdata1 signal.
FIG. 25 is a time chart showing signals inputted into and outputted from the I/O data buffer 131a (CLK signal, MASK0 signal, Rdata0 signal and Rdata1 signal).
In FIG. 25, in a period of pulse generation for a first CLK signal (period (1)), or to describe more precisely, in a first transition of a pulse for the first CLK signal, both the transfer gates SW120 and SW121 are turned ON, and when the MASK0 signal indicates a xe2x80x9cLxe2x80x9d level, namely when an operation for disabling data read is not executed and at the same time the Rdata0 signal indicates a xe2x80x9cLxe2x80x9d level, also the Rdata1 signal indicates a xe2x80x9cLxe2x80x9d level. In this case, output from the inverter 181 indicates a xe2x80x9cHxe2x80x9d level, output from the NAND gate 182 indicates a xe2x80x9cHxe2x80x9d level, and the signals are inputted to one contact terminal of the transfer gate SW120. At this point of time, as the transfer gate SW120 is ON, output (xe2x80x9cHxe2x80x9d level) from the NAND gate 182 is inputted as it is to the inverter 185.
A signal outputted from the inverter 185 is inverted to a xe2x80x9cLxe2x80x9d level, and then it is inputted to the inverter 189. This xe2x80x9cLxe2x80x9d level signal is inverted by the inverter 189 and finally becomes a xe2x80x9cHxe2x80x9d level signal to turn OFF the switching element TR120.
Output from the NOR gate 183 indicates a xe2x80x9cHxe2x80x9d level, and is inputted to one contact terminal of the transfer gate SW121. As the transfer gate SW121 is still ON, output (xe2x80x9cHxe2x80x9d levelxe2x80x9d from the NOR gate 183 is inputted as it is to the inverter 187.
A signal inputted from the inverter 187 is inverted to a xe2x80x9cLxe2x80x9d level and is inputted to the inverter 190. This xe2x80x9cLxe2x80x9d signal is inverted by the inverter 190 to a xe2x80x9cHxe2x80x9d level signal to turn ON the switching element TR121.
Thus the switching element TR120 is turned OFF with the switching element TR121 turned ON, so that a level of a signal outputted to the data input/output terminal DQ0 indicates a xe2x80x9cLxe2x80x9d level at the same potential as the potential VSS. Namely, a signal at a level indicated by the Rdata0 signal (Rdata1 signal) is outputted to the data input/output terminal DQ0.
Next, in a period of pulse generation for a second CLK signal (period (2)), or to describe more precisely, in a first transition of a pulse for the second CLK signal, both the transfer gates SW120 and SW121 are turned ON with the MASK0 signal still indicating a xe2x80x9cLxe2x80x9d level, and the Rdata0 signal indicates a xe2x80x9cHxe2x80x9d level, namely also the Rdata1 signal indicates a xe2x80x9cHxe2x80x9d level. In this case, both the Rdata0 signal and output from the inverter 181 indicate a xe2x80x9cHxe2x80x9d level, so that output from the NAND gate 182 indicates a xe2x80x9cLxe2x80x9d level and is inputted to one contact terminal of the transfer gate SW120. At this point of time, the transfer gate SW120 is ON, so that output (xe2x80x9cLxe2x80x9d level) from the NAND gate 182 is inputted as it is to the inverter 185.
A signal outputted from the inverter 185 is inverted to a xe2x80x9cHxe2x80x9d level, and is inputted to the inverter 189. This xe2x80x9cHxe2x80x9d level signal is inverted by the inverter 189 to a xe2x80x9cLxe2x80x9d level signal to turn ON the switching element TR120.
As the Rdata1 signal indicates a xe2x80x9cHxe2x80x9d level and the MASK0 signal indicates a xe2x80x9cLxe2x80x9d level, the NOR gate 183 outputs a xe2x80x9cLxe2x80x9d level signal, and the signal is inputted to one contact terminal of the transfer gate SW121. The transfer gate SW121 is ON, so that output (xe2x80x9cLxe2x80x9d level) from the NOR gate is inputted as it is to the inverter 187.
A signal outputted from the inverter 187 is inverted to a xe2x80x9cHxe2x80x9d level and is inputted to the inverter 190. This xe2x80x9cHxe2x80x9d level signal is inverted by the inverter 190 to a xe2x80x9cLxe2x80x9d level signal to turn OFF the switching element TR121.
Thus the switching element TR120 is turned ON and the switching element TR121 is turned OFF, so that a signal outputted to the data input/output terminal DQ0 indicates a xe2x80x9cHxe2x80x9d level at the same potential as VCC. Namely, a signal at a level indicated by the Rdata0 signal (Rdata1 signal) is outputted to the data input/output terminal DQ0.
Then in a period of pulse generation for a third CLK signal (period (3)), or to describe more precisely, in a first transition of a pulse for the third CLK signal, both the transfer gates SW120 and SW121 are turned ON, and when the MASK0 signal indicates a xe2x80x9cHxe2x80x9d level, namely when an operation for disabling data read and at the same time the Rdata0 signal indicates a xe2x80x9cLxe2x80x9d level, also the Rdata1 signal indicates a xe2x80x9cLxe2x80x9d level. In this case, both the Rdata0 signal and output from the inverter 181 indicate a xe2x80x9cLxe2x80x9d level, so that output from the NAND gate 182 indicates a xe2x80x9cHxe2x80x9d level and the output is inputted to one contact terminal of the transfer gate SW120. As the transfer gate SW120 is ON, output (xe2x80x9cHxe2x80x9d level) from the NAND gate 182 is inputted as it is to the inverter 185.
A signal outputted from the inverter 185 is inverted to a xe2x80x9cLxe2x80x9d level, and is inputted to the inverter 189. This xe2x80x9cLxe2x80x9d level signal is inverted by the inverter 189 to a xe2x80x9cHxe2x80x9d level signal to turn OFF the switching element TR120.
As the Rdata1 signal indicates a xe2x80x9cLxe2x80x9d level and the MASK0 signal indicates a xe2x80x9cHxe2x80x9d level, the NOR gate 183 outputs a xe2x80x9cLxe2x80x9d level signal, and the output is inputted to one contact terminal of the transfer gate SW121. The transfer gate S121 is turned ON, so that output (xe2x80x9cLxe2x80x9d level) from the NOR gate 183 is inputted as it is to the inverter 187.
A signal outputted from the inverter 187 is inverted to a xe2x80x9cHxe2x80x9d level and then is inputted to the inverter 190. This xe2x80x9cHxe2x80x9d level signal is inverted by the inverter 190 to a xe2x80x9cLxe2x80x9d level signal to turn OFF the switching element TR121.
Thus both of the switching elements TR120 and TR121 are turned OFF, and a signal outputted to the data input/output terminal DQ0 is set in the high impedance (Hi-z) state. Namely, a level of a signal outputted to the data input/output terminal DQ0 becomes unstable, and with this configuration an operation for disabling read data is executed.
Then in a period of pulse generation for a fourth CLK signal (period (4)), or to describe more precisely, in a first transition of a pulse for the fourth CLK signal, again the MASK0 signal indicates a xe2x80x9cLxe2x80x9d level and enters the state similar to that in the period (2).
Testing for checking operations of semiconductor memories including those each having a plurality of pins of data input/output terminals and also having a mask/disable terminal for selectively enabling data write and data read like the SDRAM as described above is generally carried out by using an IC tester having the terminal connection pins connected to terminals of the semiconductor memory.
However, there is a limit in a number of drives or comparators to which the IC tester is applicable, namely in a number of terminal connection pins, so that a number of semiconductor memory devices which can be tested simultaneously is limited. Especially, when in order to test a semiconductor memory device having the mask/disable terminal as described above, to test all of the semiconductor memory devices, terminal connection pins for testing must be prepared for all of the mask/disable terminals of the semiconductor memory devices, so that there is a limit in a number of semiconductor memory devices which can be tested simultaneously.
FIG. 26 is an explanatory view showing testing operations with an IC tester for a semiconductor memory according to the conventional technology, and shows how the IC tester is connected when the conventional type of semiconductor memory described above is tested with the IC tester. Although not shown in a figure, when testing is carried out with the IC tester, generally a plurality of semiconductor memory devices are set in receptacles respectively and tested simultaneously to reduce the testing time.
As shown in FIG. 26, when two semiconductor memory devices 191 and 192 are to be tested simultaneously, data input/output terminals DQ0 to DQ15 of each of the semiconductor devices are connected to a common data bus line, and also the /RAS, /CAS and /WE terminals are connected to a common control command line, so that a number of connection terminal pins of an IC tester required for the common data bus line and command control command line are sixteen (16) for the data input terminals DQ0 to DQ15 and three (3) for the /RAS, /CAS and /WE terminals.
Thus, a number of terminal connection pins required for the data bus line and control command line does not change according to a number of semiconductor memory devices to be tested simultaneously. On the other hand, each semiconductor device has two mask/disable terminals, and it is required to control the mask/disable terminals of each semiconductor memory device independently, so that totally four connection terminal pins must additionally be prepared for connection to DQML and DQMU terminals of each semiconductor memory device. When two mask/disable terminals of the semiconductor device 191 are connected to two mask/disable terminals of the semiconductor device 192, total twenty-three pins are required, and if a number of available terminal connection terminal pins in the IC tester is twenty three (23), three or more semiconductor devices can not simultaneously be connected to this IC tester for testing.
For simultaneously testing a plurality of semiconductor memory devices each having a mask/disable terminal or mask/disable terminals, the number of additionally required drivers/comparators for an IC tester can be computed through the expression: (a number of mask/disable terminals in each semiconductor memory device)xc3x97(a number of semiconductor memory devices to be tested). Thus, a number of semiconductor memory devices which can simultaneously be tested is reduced, and a time required for testing becomes disadvantageously longer. Especially, when a large number of semiconductor memory devices are tested, the problems described above becomes serious.
To solve the problem described above, it is conceivable to employ such a method as increasing a number of drivers/comparators or increasing data bus lines in a IC tester, or using an IC tester equipped with a sufficient number of drives/comparators, but such option or IC tester becomes very expensive and results in an increase in the facility cost, which is not preferable in an actual application.
It is an object of the present invention to provide a semiconductor memory making it possible for a large number of semiconductor memories to be simultaneously tested with an IC tester currently used and providing excellent convenience especially in testing.
With the present invention, it is possible to change allocation of data input/output terminals inhibited for data to be written therein or read out therefrom for each last/disable terminal, and even when use of one mask/disable terminal is inhibited, it is possible to control a mask/disable operation for the data input/output terminals allocated to the mask/disable terminal with other mask/disable terminal.
With the present invention, in the second operation mode (testing mode), a mask/disable operation for both the first and second data input/output terminal groups can be controlled with a first mask/disable terminal, so that a number of mask/disable terminals used in the second operation mode can be reduced and a number of semiconductor devices which can simultaneously be tested can be increased.
With the present invention, correspondence between data input/output terminal groups and mask/disable terminals can easily be changed according to an operation mode by switching connection between the first and second mask/disable terminals and first and second write/read control circuit sections with a changing unit.
With the present invention, by switching connection between the first and second mask/disable terminal and the first and second write/read control circuit sections with the changing units, correspondence between data input/output terminal groups and mask/disable terminals can easily be changed according to a particular operation mode.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.